We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Moore's Law and the impact of it on the industry today.
The assertion that Moore made in April 1965 Electronics
paper was:"Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below)."
"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."
Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.
The reduction of cost per component for many years was directly related to the reduction in feature size - dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2" all the way to 12".
But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:
And more analytical work by IBS’ Dr. Handel Jones
Graphically presented in the following chart
Or as nicely drawn by Globalfoundries
Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.
Looking at the other roadmap chart provided by IMEC
and focusing on the SRAM bit cell in the first row, the situation seems far worse:
Since at 28 nm SRAM bit cell is already 0.081μm2
, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.
Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:
Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349
Dimensional scaling was not an integral part of Moore's assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.
We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel debates on the answer to an important question that is on everybody's mind these days.
Like every Semicon West show in the past, where many experts are brought together for showing the latest and greatest semiconductor manufacturing equipment and bringing numerous seminar/panel discussions, this Semicon West of 2013 was no different. Two major issues were discussed, which on the face of it look unrelated, that caught my attention:
- 3D - TSV technology, and
Obviously these two issues are very different, but they are quite similar in respect to the following:
1. As the advanced node progresses to smaller and smaller feature size we are getting closer to the "end of the road map" or the "end of Moore's law".
Going to EUV does alleviate some of the problems related to the current solution of double patterning (or quadruple in the future assuming, EUV doesn't come to fruition soon enough).
As well, utilizing 3D devices with TSV has, in the grand scheme, a similar outcome; namely, advancing the integration via 3D structures rather than continued scaling. Though in the future, 3D devices and advanced nodes could go hand in hand.
2. The big miss of the road map. When one looks at some old road maps from a few years ago, one can ask how did we, the industry, miss by so much?
This actually reminds me of another miss from a few years ago-the low k inter-metal dielectric. Fig. 1 shows the low k dielectric roadmap trend of various ITRS published roadmaps and the prediction in 1999 that by 2004 we would be using k<2 !! Obviously we know what happened and even today 14 years later it is hard to breakthrough a k value of 2.5.
Figure1: low k Dielectric Road Map
Figures 2 and 3 show the roadmap for EUV and TSV, respectively. Both are of 2009 vintage. In each case the prediction of the road map vs. actual is startling.
Figure 2: EUV road map
Figure 3: TSV road Map
It is not the purpose of this blog to go over the reasons why the roadmaps of EUV and TSV missed the time table by miles, nor to blame anybody for it. There are many articles and discussions published on the subjects. Rather, I will touch on some of the highlights as well as try to make some conclusions regarding the pathway of the industry regarding these two important technologies.
EUV: The EUV technology has so far gone through monumental achievements vis-Ã -vis the incredible tasks of developing the next generation stepper technology. The amount of engineering and resources poured into it is unprecedented in the short history of the semiconductor industry and maybe so for other industries.
It looks like as I write this blog that the only barrier for the technology from becoming a HVM tool is EUV source power that can provide a high enough throughput. Many experts doubt that it could ever be achieved; however, there are many other experts saying that it is within a reach.
TSV: In this case I could see two totally unrelated issues:
1. Technology driven obstacles
2. Logistics and supply chain issues.
In the case of the TSV it is one of the few cases where the "power point" presentation(s) of the TSV idea are so convincing that it is actually hard to oppose it. However, when it comes to the fine details of the technology development, there are many issues that still need to be addressed and resolved. I believe that it is just a matter of time before the technical obstacles will be resolved and a unified standardized solution emerges. However, on the other hand, I see a real problem from the point of view of logistics, cost and supply chain of the technology, and I have some doubts if it can ever be resolved. For further discussion on this issue, please refer to: 3D IC Supply Chain: Still Under Construction
, and to a detailed comment in EE Time published blog and comments re. Semicon West 3D - IC TSV
, provided here below.
In summary, I believe that the industry will come with a solution for EUV before TSV becomes a production technology.
Yet there is another alternative to TSV and to EUV - it is the Monolithic 3D methods. Moreover, it is very likely that monolithic 3D will reach volume production before
EUV and TSV. As we already see the NAND Flash vendors ramping up for production of 3D NAND
The detailed comment fromm EE Times re. Semicon West 3D - IC TSV
| || USER RANK CEO | Re: Semicon Showed Support for 3D ICs chipmonk0
7/18/2013 1:46:13 PM
" same old same old ... " !! With such pollyannaish coverage, I am afraid that TSVs will remain the next hot interconnect tech even 5 years from now !
To provide a counter-point to all this happy talk, SemiCon had invited me to lead a 1 hr discussion at the Show on "Roadmap for TSVs and Alternatives from a Technology perspective ". Since Herb was not there, here are the key points :
1. unlike previous Advanced Packaging technologies like Flip Chip which we developed at IDMs like Motorola & Intel with both deep / broad expertise and product commitments, the development of TSVs has been going on mostly at overseas Govt. funded Laboratories in fits and starts and has then jumped to Foundries / OSATs. Xilinx' use of 2.5-d to integrate poorly yielding FPGAs has led to much irrational exuberance and then disappointment.
2. In the Winter of 2010 - 11 Samsung reported the first Wide I/O DRAM stack using TSVs. Great bandwidth even at 200 MHz & terrific power eff. But what the blogosphere neglected to report was that the yields were down in the mud and since then not much has been heard about Wide I/O from Samsung. Instead they keep bringing out conventional LP DDR at ever higher Clock Rates. JEDEC has actually postponed Wide I/O to 2015.
3. The development of TSV technology has been going on in Fabs who do not have to be sensitive to stress issues common in "thick film" type laminates / composites as is the case for filled vias. It is only now that they are waking up to it. Stress effects depend on the sq. of via dia., hence the new interest in shrinking them below 5 um. But integration & reliability problems ( at high Aspect Ratios both get worse ) have not been thought through. Moreover, Bonding stacked chips using the current method ( a sort of pidgin version of the technology I had invented nearly 20 years ago at Motorola for GaAs Power Amps that went into Cell Phones ) also introduces residual stress, affects electron mobility and shifts timing.
4. While these slow-poke Govt. funded Euro Labs rediscover stress effects on device perf. and the perils of Cu metallurgy applied indiscriminately, there is at least one small Company outside Chicago that has already shifted to the non - obvious ( at least to these TSV-niks ) yet theoretically sound choice of using Tungsten ( a brittle and poor electrical conductor which can be compensated by Design but unlike Cu a close CTE match with Si ).
5. But thats not all Folks - this tiny Co. with just 3 PhDs and Physicists has also solved the biggest TSV integration problem thats keeping all these Labs and various Tool Vendors new to the game ( in Herb's Osterreich they love to build big complex "Maschine" - Physics be damned ) -- intent on optimizing their individual process steps ( e,g. back up wafer bond / debond ) at the risk of compromising the whole process -- awake at night.
6. We did cover more, e,g. as to how to get the electrical benefits of TSVs w/o actually having to drill holes in live Silicon, circuitry and packages that make it possible. We already have some of these Alternatives ( using the concept of Active Interconnects ) under development - especially for the very large Server & SmartPhone markets - and have started publishing.
7. TSV development is orders of magnitude more complex than Flip Chip and would benefit from the same type of brutal, theory-driven Program Management practiced at the world's largest semiconductor Co., but since they have money in the Bank to stay on Moore's Law and thus continue single chip solutions they don't need TSVs that badly. So unless there is a radical shake - up in the TSV programs "outside", incl. at the Foundries, the present slow pace of TSV development will persist.
Morale : give TSVs a fair chance, they need a respite from these overly enthusiastic bloggers, embarassingly out of their depth, and at Conferences lets not blather about Supply Chain Issues, the technical probems are not all solved yet
Imec's Luc van den Hove vs. Intel's Mark Bohr
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses EE Time's article about: "Moore's Law seen hitting big bump at 14 nm".
The EE Times article
covering Imec's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase - and still carry a hefty cost premium - due to the lack of next-generation lithography". Van den Hove provided the following slide photo as an illustration:
Yet, in an article about Intel's 22nm IEDM presentation, EE Times is quoting
Mark Bohr of Intel: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel "is nowhere near that," he said. "Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but thatâs more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm," Bohr said.
So who is right between those two giants?
Could it be that both of them are?
In a recent blog titled "Is the Cost Reduction Associated with Scaling Over?"
we presented charts clearly supporting Luc van den Hove, IMEC's CEO, position. The following slide from an IBM presentation includes an NVidia chart (which we also discussed in another blog, Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies?
Accordingly, it would seem that TSMC wafer costs are in line with Luc and so is the case with IBM.
GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium yesterday (Dec. 11) also acknowledged that their 14nm node will have a 20nm node metal pitch and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
In other words, it seems that the Luc van den Hove keynote is in-line with the cost road map of the non-Intel foundries!
Intel might indeed be different, yet something did cause Intel to take what seems like an extreme measure, when it put $4.1B in ASML just recently
If, however, Mark Bohr has not been misled by the Intel accounting department, and the Intel process is still providing a nice cost reduction at every node of scaling, then clearly Intel has a true competitive edge relative to all other foundries. I have no doubts that Intel has filed enough patents to protect its unique process advantage, but then I wonder why did Mark say
: "However...we don't intend to be in the general-purpose foundry busines ... [and] I don't think the [foundry] volumes ever will be huge [for Intel]."
If Mark Bohr is right, with such a competitive edge Intel should aggressively expand its foundry business, which would achieve both a great profit margin and rapid business growth. Now that Intel is looking for a new CEO its Board should consider it as a major criterion for who should lead Intel into the future.
Clearly, dimensional scaling (and its cost reducing benefits) is not what it used to be, and the market appetite for cheaper-faster-better consumer-oriented products grows stronger. Both Intel and non-Intel fabs should start development of monolithic 3D technology. ;-)
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about Qualcomm overtaking Intel in market capitalization.
On Nov 9, 2012 we learned that Qualcomm overtook Intel in market capitalization. Quite shocking news if one considers that Intelâs revenue is almost three times that of Qualcomm and its net margin is more than twice that of Qualcomm. Clearly investors evaluate Qualcomm using a different scale than what they use for Intel, as is evidenced by Qualcommâs P/E of 20.12 vs. Intel's mere 9.07. EE Times explained it in an article that day stating: "In the eyes of investors who have driven up its market capitalization, the fact that Qualcomm is a fabless company relieves it of the burden of having to invest billions of dollars each year in process development and wafer fabs." However, given that TSMC, a pure foundry, has a P/E of 15.67, it behooves us to look for another explanation. Itâs also worth noting that TSMC had a revenue growth of 2% in the last year, far less than Intel's 25.6%, and its net income actually went down vs. a net income growth by Intel of 213%!
My explanation is that it is all about IP strength. I will expand on it in the rest of this blog but as prime evidence I offer SanDisk, who sports a P/E of 20.78 yet has continued to invest heavily, together with its partner Toshiba, in fab capacity upgrades.
Letâs first look at the previous two decades as Intel grew consistently year after year while riding the PC business growth. During those years the team Intel + Microsoft was the exclusive vendor in the PC 'game'. All others had to compete neck to neck in this fast growing commodity market. And as we all know, broad competition erodes margins and allows only the lowest cost producer to achieve some profits. In the case of PC this erosion actually pushed out the market creator - IBM - which eventually exited the market and sold its business to Lenovo. The only real winners back then were Microsoft and Intel, who had pivotal differentiating IP. Yes, Intel had a licensor - AMD - but as a licensor, AMD had to pay heavy royalties that impacted its profits, and helped those of Intel.
Both Intel and Microsoft were able to leverage there unique IP into years of growth and became the largest companies in their field.
But being the largest today does not guarantee the tomorrow. Or, as Andy Grove famously said, "only the paranoid survive".
The technology world is about change. While many of the changes are incremental, at times the paradigm changes too. The change that took away Intelâs and Microsoftâs unchallenged market and IP position was the shift to "smart mobile," or mobile internet, as is illustrated in the following chart.
The technology world is about change. While many of the changes are incremental, at times the paradigm changes as well
And with these changes new technology leaders have been emerging: companies such as Apple, Qualcomm, and Google.
To make matters even worse, a small company - ARM - was able to create a disruptive change in the computing engine with its preferred computing architecture, first for 'smart mobile,' then for tablets, and now it seems to penetrate the PC and the server markets.
In my view, as soon as the investment community realized that Intelâs exclusive market and IP position is not relevant to the new market of Mobile Internet, it started to tune down Intelâs P/E. This trend even got stronger as investors became concerned regarding Intelâs position in the PC and server market.
It should be noted that in this context IP is not counted by the number of patents or the amount of trade secrets but rather by the ability to exclude competitors from major markets or extract royalties from those competitors, which may make you a winner even when you loose business. This is a status that Qualcomm and other companies such as SanDisk enjoy.
Economists estimate that two-thirds of the value of large businesses in the U.S. can be traced to intangible assets.
"IP-intensive industries" are estimated to generate 72 percent more value added
(price minus material cost) per employee than "non-IP-intensive industries".
[dubious â discuss
] , as is illustrated by the following chart
So, is the game over for Intel??? Is the Market irrational, or is the Market perceptive?
Some pundits clearly think so, but given its leadership semiconductor technology, strong leading edge manufacturing infrastructure, and balance sheet, it is way too soon to call game over for Intel. But it would seem that Intel needs to introduce some real change in order to correct its course. Perhaps Intel should look back at what Andy Groveâs said and ask itself: does it really act like a paranoid company, or perhaps it is just the inverse.
We at MonolithIC 3D believe that the whole semiconductor industry is about to go through a major disruptive change. After 50 years of successful growth and progress by dimensional scaling, the time has come for a direction change, and the time is now for starting to embrace scaling-up, going for monolithic 3D. The current leaders in dimensional scaling, the NAND Flash vendors, seem to be leading the way. They are pushing ahead with monolithic 3D-NAND. This disruptive change will bring vast new opportunities, and those who will be early to embrace the change may be able to reap the IP reward.
We have a guest contribution today from Iulia Morariu, who works in our Romanian team. Iulia is an energetic and creative person who has been doing great things for our marketing division. She will give a thanksgiving greeting.
As you'd know, Korean companies such as Samsung and Hynix contribute 50-60% of the world's memory revenues. In today's blog post, we’ll look at reasons and strategies behind this dominance...