Semiconductor Manufacturing & Design has a very interesting discussion of the ways that die stacking will impact final product yields.
According to the report in EETimes, the group of companies contributing to the 3-D enablement program at SEMATECH has just grown by six.
From what I hear at meetings, Qualcomm is one of the companies really driving towards production of 3D chips/packages. Of course, it makes perfect sense given their commitment to the mobile market, with its attendant constraints on power and footprint combined demands for significantly better system performance.
Dr. Garrou has an excellent post that includes a segment on work at Penn State and IBM on the ways that dense TSVs can impact thermal management.
The DAC Blog has a very nice report on Dr. Walden Rhines' discussion of 3D ICs at the recent GlobalPress event. The post presents more details than I've seen in other reports. If you're interested in seeing what one of the true EDA luminaries is thinking about 3D, go read this post...
Electronics Weekly has an interesting story about a pile of EV Group (EVG) equipment going in to a 300mm line at CEA-Leti.
We tend to approach the world of 3D IC from the perspective of technology innovators, so it's always interesting for me to hear the perspectives of the design tools community as well as the semiconductor companies actually implementing solutions. That's why I particularly appreciated Richard Goering's report covering the IEEE Electronic Design Processes (EDP) workshop.
Paul McLellan made an interesting series of posts over on his edagraffiti blog a while back. If you're interested in the EDA perspective on 3D ICs, you should go check them out. You probably should go read them just because Dr. McLellan is a great writer who always adds value with his observations. His list of relevant posts includes:
EETimes had a nice report on the recent International Symposium on Physical Design (ISPD), held March 27-30, 2011 in Santa Barbara, CA. For our purposes, the particularly interesting bits were: