We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about MonolithIC 3D Inc.'s participation at Semicon West 2013.
Thanks to everybody who came by poster exhibition at the Silicon Innovation Forum at SemiconWest 2013 [SemiWest]
! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.
Here is Zvi 'guarding' the poster:
Figure 1 - Zvi Or-Bach at Semicon West 2013
Atoms Don't Scale: Dennard type scaling is already reached diminishing returns and looks like going to 'hit the wall' near this decade's end. P. Farrar of IBM said it succinctly: Atoms Don't Scale, and Steve Punta of Intel said "hard to imagine good devices smaller than 10 lattices across - reached in 2020":
As well, Bob Cowell of Intel microprocessor fame, who is currently the head of DARPA's MTO (Microelectronic Technology Office)...the folks who are supposed to be looking way ahead...is publicly saying that Moore's Law is at its end and we will have (at least) a decade long gap (2020-2030) in device improvements:
We all know the trends...much higher lithography costs and litho driven defects, interconnect resistance and capacitance slowing performance, the connectivity is driving power budgets awry, and so on. And the result is that the historical cost trends that we have been enjoying are going to soon no longer be there. Will carbon nano-tubes, graphene, nanowires, InGaAs, spintronics,... save us? Not likely, and certainly not by 2020. What's the Answer?
Monolithic 3D can utilize the existing infrastructure, so the usual 5-10 years of development of evolutionary concepts places this solution as being capable for answering the 2020 call. TSVs (parallel 3D), if
the costs can be contained, can only address a very small part of the solution space.
Take a look at the monolithic 3D techniques and potential for more than Moore ever predicted. http://www.monolithic3d.com/3d-ic-edge1.html
As an industry, how are we going to fill the decade gap?
Give me a call or email if you want to talk more...
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses how can heat be removed from 3D-IC Stacks.
Thanks to everybody who came to IEDM
this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei
University. You can find the meeting paper and slides here
One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing proposed techniques rely on arrays of TSVs and thick (xxum) silicon layer to conduct and spread the heat laterally and vertically. We propose that properly designed PDNs* (Power Delivery Networks) can significantly contribute to heat removal in both parallel (think TSV and xx um thick Si layers) and monolithic/sequential (think 100nm Si layer) 3D-ICs.
We investigated both parallel and monolithic in the paper. Here, I will, of course, focus more on the monolithic challenges and solutions, but I will make some important comparisons to parallel at the end.
Since the 130nm node, we have entered an era in our industry where we are not only using new materials, but also new device structures. I have written previously
about the risk associated with this, and (hopefullyâ¦) made a case for monolithic 3D technology being the best way for the industry to move forward, still enjoying Mooreâs Law type economics (i.e., lower cost) but with a much lower development risk.
Life is getting thin and narrow in our businessâ¦.so, how best to take advantage of this nanometer and angstrom era and avoid the economic (think EUV at 110+M$ a pop, or double/quad patterning) and atomistic (think 7 nm) brick walls coming? Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab
, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly processes of TSVs.
One of the basic tenets of monolithic 3D is the ability to have thin (preferably monocrystalline) silicon layers that enable very small vertical interconnect manufacturing, and hence a large (>1 million/cm2) layer to layer vertical interconnect density in the stack. This opens up the possibility for powerful new architectures and devices, such as Amdahl's wafer scale computer (see blog
) and cost effective MLC 3D memories
Two implications arise from the thin (on the order of 100nm or less) silicon layer stacking. First, that fully depleted (FD) devices, and hence silicon islands floating in an insulator such as silicon dioxide, will be the norm. Second, taking full advantage of a manufacturable aspect ratio etching (5:1 to 10:1), we will end up with a large density of very small layer to layer vias (of 1-2 lambda diameter), where vertical interconnect density rivals the horizontal density of interconnect that we have enjoyed thru the many cycles of Dennard
scaling. FD devices are soon to be the norm in 2DICs; for example, the thin UTBBOX
of STMicro/GlobalFoundries and the narrow FinFets
(incidentally, at IEDM12, Intel was criticized for doping the finsâ¦).
Both of these implications, FD devices in islands of Si and very dense vertical interconnect, play a significant role in how we propose to solve a major challenge in 3D stacking.
Since the stacked layers are not in direct contact with the heat sink: How do we get the heat out of the stacked layers???
In short, the answer is to take the heat out of each silicon island with the power delivery network, move it laterally in the metal interconnect of that stack layer (just as if
we had a thick silicon layer underneath), and then vertically move the heat to the heat sink with that large density of interlayer vias (which we can now make due to the thin stacked layer being very thin).
Hereâs a picture of what we are doing:
Sounds at least plausible, right?
Well, thatâs what we set out to show, with the heavy lifting done by our friends at Stanford. Hai Wei & Tony Wu of Professor Subhasish Mitra's group
, Professor Mitra, and Professor Fabian Pease
, were the drivers in creating the simulation approach and engine to see if this works as we thought it might. It did, and then ended up developing a tool that may be very useful for future 3DIC design work.
Hai and Tony describe in the paper and the presentation the details of the simulation approach, engine, assumptions, and methodologies developed. Quite a nice piece of work! They have built an analysis framework that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs. Types of 3DIC
technologies modeled are conventional TSVs
, called parallel 3D integration by many in the industry, and monolithic 3D integration, a type of sequential 3D integration. Cooling options range from conventional air cooling of the heat sink (2 W/KÂ·
cm2) to external liquid cooling (10 W/KÂ·
cm2) for high power systems. PDN designs studied ILV densities from 0 to 4 million/cm2.
That said, what are the essential takeaways?
First, the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Without accounting for PDNs in the 3DIC thermal model, it will be next to impossible to achieve the desirable thermal characteristics and result of a 3D IC stack. Further, the density of ILVs is important to achieving the system thermal constraint. In the 100nm thick Si example below, the desired maximum chip temperature is 85Â°C or less.
Second, a processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration. Hai and Tonyâs thermal analyses of core-on-core and memory-on-core designs, utilizing the OpenSPARC T1
industrial multi-core design operating running an 8-threaded program that solves the Black-Scholes
application (i.e., hot), showed significant improvement and no hot spots. The top silicon layer is 100nm thick and the hottest parts of the chips were operating at 138 W/cm2. Those hottest parts, the EXU units, were stacked directly on top of each other to show the worst case.
Combining these two seems to indicate that no PDN in the model versus designing and optimizing with thermal-aware PDNs makes the difference between being able to run the design (processor on processor in this example) at only 1/3 of the full power density or at a full power.
Thatâs the essential take-away for monolithic. Mimic the lateral heat conduction of thick silicon with the PDNs of the thin silicon stack layer, and then get that heat vertically to the heat sink with the dense network of vias provided by the monolithic 3D integration.
For the parallel 3D integration case, the 5um thick silicon greatly helps with the lateral heat conduction to the TSVs. With a properly designed PDN; however, there can be a significant savings in the number of TSVs (ILVs on chart below) used to vertically conduct the heat away, and thus offers a significant area savings by eliminating many of those big TSVs and Keep Out Zones (KOZs). (Note: for both the parallel and monolithic cases, Hai made the KOZ twice the ILV diameter as a conservative choice)
Moreover, by use of a properly designed PDN and an optimized density of TSVs, the maximum power density of the top layer in can be increased considerably â¦. from 35 to 50 W/cm2 for the parallel 3D case.
It is worth noting an important point from these graphs: At the optimum design point, where the density of ILVs coupled to the PDN satisfies the desired 50W/cm2 max allowed power density, the required number of TSVs to effectively conduct the heat costs about 3% of the chip area. For the monolithic case, the chip area cost is about half that.
A high density of small vias not only makes possible some powerful product architectures such as logic-cone level redundancy, but is also key to producing area efficient vertical heat conduction networks.
*Patent Pending technology
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses low temperature cleaving.
Thanks to everybody who came by our booth at SemiconWest SemiconWest 2012
this second year! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.
For those who could not make it, here is what our booth looked like:
Nice tie again Zvi! You can still visit us at www.monolithic3d.com
The most common area that you asked us was about low temperature (less than 400Â°C) bonding and low temperature cleaving processes. The two topics are quite inter-related: One must make the bond stronger than the energy it takes to cleave at the plane you want, rather than cleave at th at fresh bond. In October last year I wrote a blog about the many low temperature bonding techniques and strategies available and their respective bond strengths. Today, I would like to briefly address some of the low temperature cleaving methods available. Generally they involve either a mechanically induced (blade, gas jet, water jet) method, a lower temp thermal (co-implantation, microwave, etc.) cleaving/layer-transfer method, or a combination of both.
Here are a few papers, with some industrial announcements at the end.
One of the earliest methods published is co-implantation by Q.Y. Tong et al
. of Duke University at the 1997 IEEE SOI Conference
. Tong could greatly affect the kinetics of the hydrogen blister formation by co-implantation of Boron. They were able to transfer a 0.4um silicon layer onto a quartz substrate with a 150Â°C exposure to the quartz by pre-annealing the co-implanted silicon for 10 minutes at 250Â°C.
Tong with colleagues at the Max-Planck-Institute followed up with more co-implantation
kinetics data in a 2008 Applied Physics Letter. They again demonstrated a 200Â°C silicon cleave.
In 1998 App. Phys. Lett., Agarwal et al. showed that He implanted with the H could lead to a significant decrease in the total implant fluence (and hence cost) necessary to achieve Si layer transfer. The total implantation dose can be three times smaller than that which is necessary using H alone.
Nguyen et al. of Soitech/CEA-Leti, at the 2003 IEEE SOI Conference showed that He co-implantation could be used to control the kinetics, so time, dose and temperature trades could be made.
Ma, et al. showed in Semcond Sci. Technol. 2006 that a co-implanted cleave has a smoother
surface than a hydrogen-only implanted cleave.
In 2000 App. Phys. Lett., Henttinen et.al showed mechanical cleaving, blade or N2 gas, on low temperature bonded silicon wafers (ox-ox bond). Depending on the H dose, Henttinen could
cleave the silicon wafers at 200Â°C or 300Â°C. Henttinen et.al followed up later in 2002 in J. Nucl. Instr. and Meth. in Phys with fundamental mechanistic studies and also demonstrated that with enough B doping one can enable H-implanted layer exfoliation below 200Â°C.
Cho et al., in 2003 App. Phys. Lett. reported that full wafer layer transfer could be achieved with a mechanical cleave (edge initiated crack propagation) after a 250Â°C annealing that enabled the bonding strength at the acceptor/donor interface to exceed the required cleave energy at the hydrogen implant plane.
En, et al., of Silicon Genesis, described a room temperature H implant using PLAD (Plasma Immersion Ion Implantation), plasma assisted oxide to oxide bonding, and a room temperature mechanical cleave process at the 1998 IEEE SOI Conference.
Current, et al. of Silicon Genesis, showed a wafer separation tool in MRS 2001 where they utilized a pressurized N2 jet to cleave silicon bonded pairs at room temperature.
Recently from the industrial side: Soitec
announced at SemiconWest 2012
the availability of a room temperature smart cut:
"Soitecâs low-temperature Smart Cut process uses oxide-oxide molecular bonding and atomic-level cleaving to transfer mono-crystalline silicon films as thin as 0.1 micron onto partially or fully processed wafers. On this new material layer, a second level of devices can be processed and this integration can be repeated in an iterative mode. Transferring an extremely thin layer enables higher interconnect density, higher signal throughput and simpler TSV processing. Benefits include increased computing bandwidth, lower overall manufacturing cost, and power savings due to the reduced wiring distance between connected devices. This final benefit is well suited for producing advanced memory or CMOS logic 3D IC systems.â See: http://www.soitec.com/en/news/press-releases/article-346/
SiGen (Silicon Genesis) has tools (some shown above) available that will bond and cleave at or near room temperature: http://www.sigen.net/semi_debondCleave.htmlReferences:
TONG, Q.-Y., et al., "Low Temperature Si Layer Splitting", Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp. 126-127
TONG, Q.-Y., et al., "A ââsmarter-cutââ approach to low temperature silicon layer transfer", Applied Physics Letters, Vol. 72, No. 1, 5 January 1998, pp. 49-51
AGARWAL, A., et al., "Efficient production of silicon-on-insulator films by co-implantation of He+ with H+'" Applied Physics Letters, vol. 72, no. 9, March 1998, pp. 1086-1088.
NGUYEN, P., et al., "Systematic study of the splitting kinetic of H/He co-implanted substrate", SOI Conference, 2003, pp. 132-134
MA, X., et al., "A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding", Semiconductor Science and Technology, Vol., 21, 2006, pp. 959-963
HENTTINEN, K. et al., "Mechanically Induced Si Layer Transfer in Hydrogen-Implanted Si Wafers," Applied Physics Letters, April 24, 2000, p. 2370-2372, Vol. 76, No. 17.
HENTTINEN, K. et al., "Cold ion-cutting of hydrogen implanted Si," J. Nucl. Instr. and Meth. in Phys. Res. B, 2002, pp. 761-766, Vol. 190.
CHO, Y., et al., âLow Temperature Si Layer Transfer by Direct Bonding and Mechanical Ion Cut,â Applied Physics. Letters., vol. 83, no. 18, November 2003, pp. 3827-3829.
EN, W. G., et al., âThe Genesis ProcessTM: A New SOI wafer fabrication methodâ, Proceedings 1998 IEEE International SOI Conference, pp. 163-164 (Oct. 1998).
CURRENT, M. I., et al., âAtomic-layer Cleaving and Non-contact Thinning and Thickening for Fabrication of Laminated electronic and Photonic Materialsâ, 2001 Materials Research Society Meeting, April 16-20 2001, Paper I8.3.
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses why he believes Monolithic 3D-IC could be less risky than scaling or TSV.
I recently saw this great 5 minute video by Applied Materialâs Richard Lewington [AMAT 3D Blog Video]
where three types of 3D-IC construction are demonstrated. Note that the first two 3D-IC options he shows (with those plastic blocks) are monolithic. Only the third option is TSV based.
Whatâs going on here? Why is this major equipment vendor talking about monolithic 3D when it seems
that most of what the industry is talking about these days are scaling, interposers, and Thru-Silicon-Vias(TSVs)? Letâs take a look.
Being a fab-guy (built parts of and worked in Chartered Fab-1 & Fab-2, Sierra Semiâs fab inside National Semiâs Bldg#4, AMI Poci Fab-4, Synertek Fab-3, etc.) I am going to approach this from a process/fab-rat perspective. Because this is a key point to what monolithic 3D is about: it is supposed to bring 3D-IC back into the wafer batch economics of semiconductor processing. No piece part handling expense, TSV/interposer reliability & cost issues, or OSAT troubles (I applaud TSMC for trying to remedy this OSAT part, but am surprised that Global Foundries did not do it firstâ¦.they could have beaten TSMC to the punch here).
The major rule for wafer fabs is Take no Risks
â¦.. Everything you do is focused on control: understanding, eliminating, controlling variables. Protect and preserve that huge capital investment so you can pay it down. By definition & nature, fab managers are very conservative. But scaling forced us to do dramatically different and risky things. Thatâs a major reason why it takes 10+ years for new process/technologies to get into a large production fab. Think about HKMG, Cu BEOL, CMP, strain, plasma metal etching rather than wet (caused lots of corrosion issues/mousebites), to name a few. Even platen cooling (instead of aluminum mask layers) for high current implantation took a long time. Changing from flats on the starting material wafers to the notch took about 10yrs too.At its root
, many of these changes took new machines, new chemistries, and/or new process methods (think APCVD, LPCVD, UHVCVD, PECVD, SACVD, ALCVD, MOCVD, RTCVD, â¦..) Another large risk factor with scaling has been the use of more elements of the periodic table to solve scaling challenges. We did not just alter the form or compound of a known element (bad enough risk-wise); we changed to and added new elements to our expensive wafer fabs. (In fab parlance, all this ânewnessâ added up to what is called the Sphincter Effect
When I started in the industry we used only six elements from the periodic table:
Here is the current periodic table usage:
Yet, all of us scientists and engineers, as well as fab managers, solved the problems caused by relentless scaling, and the industry grewâ¦we had a lot of fun, we were supremely challenged, and we solved those challenges. But we also grew grey hair and permanently pinched sphincters.
At what cost? (remember, low cost is crucial to successful manufacturing!)
Hereâs what Global Foundries showed about costs:
So, now we have now included the investment and banking communities into our Sphincter Effect.
Enough! This is the road to ruin; well, at least to vastly diminishing returns (think Handel Jonesâ chart [ElectroIQ link to ISS12 Day 2]
on how transistor cost is no longer going downâ¦)
3D-IC is the solution. OK, soâ¦. monolithic or TSV or interposer? Above I already mentioned a few of the risks and costs to a TSV/interposer solution. Look at all the new processes and machines that had to be developed to etch and fill such deep holes at least somewhat economically. And the integration issues are significant because of the novelty and the architecture & flow: Cu/silicon stresses, keep out zones, liners, new reliability fail modes, etc. As usual, these issues will likely be solved; hence, TSV & interposers will be useful for obtaining some cost and functional/architectural gains from its limited vertical connectivity. But they are not the endgame. To get fully back onto the economic scaling path we need rich vertical connectivity.
What about monolithic 3D-IC risks & costs? Fab equipment and unit processes exist. No new elements from the periodic table are necessary. And the gains resulting from this dense vertical connectivity keep us on a scaling equivalent path (no need to spend space hereâ¦lots has been written about this). Letâs instead look at the process details:
Oxides for ox-ox direct bonding: Deposited oxides are well understood and cheap. No new equipment or elements are needed. Lots of manufacturing proven techniques to get there: PECVD, SACVD, etc.
H Implant: Can be done on current models. No new equipment needed. Done by SOI manufacturers for 20 years. H in silicon is well understood.
Bonding: Two well-known equipment vendors (EVG & SUSSMicroTec) with low temp oxide to oxide bonding capability and significant sales of machines (mostly to BSI sensor folks at this time). A recent third new entry (MHI-Mitsubishi Heavy Industries) with room temp
ox-ox bonding. I recently blogged on this topic too. [BC LT direct bonding]
Cleave: Lots of methods proven for SOI manufacture, sensors, and solar. Simplest is thermal â¦ just use a furnace or RTP. We made a short movie clip showing how simple cleave is with the AG RTP at Stanford.
Monolithic 3D-IC uses existing wafer-fab equipment, needs no new elements from the periodic table, and utilizes well-known unit processes and chemistries.
Whatâs the catch? Itâs the integration. Integration work (blood, sweat, and tears
) will always be there, even with no new elements, machines, chemistries, etc. Always. However, those who have done new process introductions know that integration is significantly
less risky (= costly) and faster to market without than with the elements/machine/chemistry changes. New modes of defect generation are always generated from integration, but there are a lot less of them if all the unit processes are standard accepted practices, than if those unit processes are totally new.
If you look very very carefully at the MonolithIC 3D Incâs process flows, you notice we were single mindedly focused on making it simple. For example, the nm-scale thru layer vias (TLVs) are always made thru the STI (Shallow Trench Isolation); hence, no dielectric liners, minimum stress, conventional etch and fill, nothing high aspect ratio about it. Make the TLV look and feel like a regular metal to metal via.
This shows in the costs. Deepak Sekar did a SEMATECH based cost estimate and talked about it in a blog. [Deepak Blog ion-cut cost]
Hereâs his summary chart for 300mm wafers.
Validation of Monolithic 3D
One may make the argument that validation of a nascent & new game-changing technology is impossible, or at least very nearly so. However, for monolithic 3D-IC there are at least two important data-points to consider. And I hope that you will be convinced that monolithic 3D-IC is neither so nascent nor new.
NAND Memory Makers going 3D: People such as David Lammers of Semiconductor Manufacturing & Design Community [Lammers July 2011]
have pointed to validation evidence that the time of monolithic 3D-IC is near: the bleeding edge NAND memory makers are already moving to monolithic 3D-IC.âThe advent of 3D NAND memories may be only two or three years away, speakers said at Semicon West in San Francisco. By 2013 the major memory companies developing 3D NAND, including Hynix, Samsung, and Toshiba, may be ready with pilot lines, moving to volume production a year or so later. Taiwan-based Macronix International also has been developing a 3D NAND solution.â
At the recent (2011) VLSI Symposium J. Choi of Samsung showed their view of how they will keep on making cheaper bits â¦ by going 3D monolithically.
Second, the global semiconductor equipment leader, AMAT, has talked about sales into that market [SemiconWest2011-new products including 3D architecture support][OptivaCVD for BSI]
and even has a video (Richard Lewingtonâs blog video noted above) to promote it.
When both manufacturers and equipment suppliers are talking about, committing to, and executing on a specific technology change, you know that the economics are attractive and not just niche. Think back to how HKMG and copper BEOL came to production.
The chicken and egg are out the window
â¦.itâs happening now. The risks are contained. Others are going for it.
Whether polysilicon or monocrystalline silicon based monolithic 3D, jump in and be a part of this next important evolution of our great industry.Donât miss out.
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses how value of a company's patent portfolio can be quantified.
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology. Brian shares his perspective on Low Temperature Wafer Direct Bonding, where an important concern is the strength of the wafer to wafer oxide to oxide bond.
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology. Brian shares his perspective on the "education and immigration debate" that's been happening on our blog the last two Thursdays...
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology. He gives an update on our company's Semicon West activities.
We have a guest contribution today from Brian Cronquist, our VP of Technology. Brian reports on his trip to Whistler, Canada, for the CMOS Emerging Technologies Workshop.
We have a guest contribution today from Brian Cronquist, where he talks about innovation he has been involved with in his career. He also talks about the first year of NuPGA/MonolithIC 3D Inc.'s existence, when the company was focused on FPGAs, and discusses how the transition to Monolithic 3D began.