IEEE International Solid-State Circuit Conference Feb 17-21, 2013 just ended at San Francisco last week, and the issue of dimension scaling as it relates to EUV and future per transistor device cost was an important item in the plenary session. But the issue of scaling as it relates to the SRAM was an important item in many of the session as we will farther discus herein.

As widely reported Martin van den Brink ASML Executive VP & CTO articulate that without EUV cost of logic transistors is most likely go up with scaling as was illustrated by his following slide:

The above slide was presented after Martin had presented another non encouraging slide, showing a Broadcom chart of increasing cost per gate with dimension scaling together with Nvidia famous chart of no more crossover of transistor cost below 28nm and GlobalFoundries chart showing some limited value for EUV:

We may attribute Martin statements to ASML interest of promoting EUV, but since ASML already received significant EUV participation from INTEL, Samsung and TSMC it might indicate farther problems on the road to bring EUV to the market. We don't know if EUV is ever become real but we already know very well that it is been delayed and delayed again. It was made public recently that it probably already missed the 10nm process node.

The real interesting slid presented by van den Brink is the following:

This chart brings up an important aspect of dimension scaling that was not discussed much before - the scaling of the SRAM bit-cell.
Accordingly the SRAM bit-cell size might not be reduced from 20nm to 10 nm and might even get larger at 7nm as it may need more than 8 transistors.
Modern logic devices needs significant amount of embedded SRAM in fact more than 50% of the logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010)

The dominating embedded SRAM bit-cell used to be the 6 transistor cell. This cell was for many years hand crafted using special design rules by the foundries for every new technology node. But the SRAM cell is a unique structure that is not obeying normal logic design rules as it use output against output any time a write cycle is been performed. In many cases it is the cell that is the most sensitive to the process parameters (as been represented by the SPICE deck) and highly impact end device yield. It well known that scaling the SRAM bit-cell had become harder and harder. Some vendors had already moved away from the 6T (six transistor) to 8T (eight transistors) bit-cell as we could have learn in this ISSCC by the number of papers the were presenting 8T SRAM. And even those the kept the 6T had presented extra support circuits to enable it.

As SRAM bit scale is becoming less than 50% we had seen in the past, the end device scaling cost could be even more disappointing than the transistor or gate cost illustrations above.   

Well aware of this IBM had been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that at 32nm product line IBM use of the embedded DRAM gave them the equivalent of process node benefits. Yet as of now most other vendors had not adapted the eDRAM due to process complexity it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimension scaling as the DRAM capacitor will be very hard to scale, the extra power for DRAM is not available and the cost of advance process development is too high to add in extra complexity.

Accordingly we could learn from these recent ISSCC that dimension scaling is facing the cost challenges we were aware of before plus one that we have might been less aware of but could hit us both on cost and on power due to the incompatibility of the 6T SRAM  bit-cell with scaling.

As we suggested before, now that monolithic 3D is practical, we could advance and maintain Moore's Law by augmenting dimension scaling with 3D IC scaling, allowing depreciation and advance engineering to bring down costs and improvements to power and performance. And additional option is to replace the 6T SRAM bit-cell with the 1T - two stable states floating body memory cell invented by Zeno Semiconductor. The Zeno bit-cell is getting better with scaling save ~80% of the silicon area and require far less power, yet it provides two stable memory states, and would work on existing logic process.

The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:

• On chip interconnect
• Lithography

These two challenges connect very well with our recent blog IEDM 2012 - The Pivotal Point for Monolithic 3D IC. Gary showed both the exponential increase of RC which results from the dimensional scaling of copper below 100nm width and the high cost associated with double and quad patterning. In addition, he showed how the extreme scaling of the copper metallization creates reliability challenges such as fatal EM modes, and scaling of the insulator k breeds TDDB and strength issues. As a reminder, in the recent IEDM (Dec. 2012) short course, IBM presented the following slide indicating that interconnect now dominates device power!

Gary also presented a multi-decade past to future slide that resembles the one presented here below. The decade ending at the year 2000 was the good old days of easy scaling of planar transistor, which he called the gate oxide limit. Then the industry followed with a decade of "Material Innovation" that he called the planar device limit, and starting in 2010 is the beginning of the "3D Era" - 3D transistors and stacked devices.

Finally he shared with us his vision of 3D devices with three planes of devices:

• Logic Plane
• Memory Plane
• Photonic Plane

A vision we mutually share.

Now, here is my failure to understand. As a company who has been in the forefront of 3D and TSV research, IBM is well aware of the severe limitations of TSV as an alternative for vertical interconnect. The following cross-sectional picture by IBM, presented at the recent GSA Summit, clearly illustrates how large a TSV is in comparison to an interconnect via.

With TSVs of 5 micron diameters (and pitches of 15 micron due to keep out zones from stress issues) vs. vias of less than 50 nm, the ratio in vertical connectivity is 1:10,000 as illustrated in the following chart by Perinne Batude of CEA Leti.

Clearly IBM technologists are well aware of the many research papers showing that TSVs, with their relatively huge size compared to all the other on-chip elements, diminish the performance or power benefits in folding designs to 3D. For example, the chart below was presented by Kim at the 2011 IEEE International Interconnect Technology Conference. The chart illustrates the performance benefits of folding a design twice (4 tiers of transistors) as dependent on the via size. At a via size of 5 microns there are actually no benefits, while at a via size of 0.1 micron the benefits are the equivalent of two nodes of dimension scaling!!!

So can someone please explain to me how come IBM is still talking about TSV as if it is the only representative of the "3D Era"???

And particularly now, when monolithic 3D is finally practical, and the NAND Flash memory vendors are adopting it across the board!?

From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:
We start with the EE Times article IEDM goes deep on 3-D circuits, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS" organized by Wilfried Haensch, of IBM’s Watson Research Center:

We then continue with statements made by Dr. Howard Ko, a Senior Vice President and General Manager of the Silicon Engineering Group of Synopsys in his 2013: Next-generation 3-D NAND flash technology article:

In our recent blog 3D NAND Opens the Door for Monolithic 3D we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart: 

And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.

This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.
The Current 2D-IC is Facing Escalating Challenges:

•  On-chip interconnect (#1)

1. Dominates device power consumption
   
2. Dominates device performance
3. Penalizes device size and cost

• Lithography (#2)
  

1. Dominates Fab cost
   
2. Dominates device cost and diminishes scaling benefits
   
3. Dominates device yield
   
4. Dominates IC development costs
   

The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:

In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:

It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.

The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:

Copper, however, is now reaching its inflection point as was articulated in a special session organized by Applied Materials attached to this IEDM, The 14 nanometer node is expected to be an inflection point. Quoting from the abstract:

This had been illustrated before in the following chart

And to make it crystal clear, IBM presented the following chart in its short course:

Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.

As for the second challenge – lithography – we start again with an old chart by Synopsys:

The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.

The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.

This resulted in the following slide by IBM at the GSA Silicon Summit 2012:

Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends" 

Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC,  IEDM: Moore’s Law seen hitting big bump at 14 nm, repeats the same conclusion. In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost. So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore's Law, would be achieved by leveraging the third dimension.

Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below

Thanks to everybody who came to IEDM this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei of Stanford University. You can find the meeting paper and slides here.

One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing proposed techniques rely on arrays of TSVs and thick (xxum) silicon layer to conduct and spread the heat laterally and vertically. We propose that properly designed PDNs* (Power Delivery Networks) can significantly contribute to heat removal in both parallel (think TSV and xx um thick Si layers) and monolithic/sequential (think 100nm Si layer) 3D-ICs.

We investigated both parallel and monolithic in the paper. Here, I will, of course, focus more on the monolithic challenges and solutions, but I will make some important comparisons to parallel at the end.

Since the 130nm node, we have entered an era in our industry where we are not only using new materials, but also new device structures. I have written previously about the risk associated with this, and (hopefully…) made a case for monolithic 3D technology being the best way for the industry to move forward, still enjoying Moore’s Law type economics (i.e., lower cost) but with a much lower development risk.

Life is getting thin and narrow in our business….so, how best to take advantage of this nanometer and angstrom era and avoid the economic (think EUV at 110+M$ a pop, or double/quad patterning) and atomistic (think 7 nm) brick walls coming? Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly processes of TSVs.

One of the basic tenets of monolithic 3D is the ability to have thin (preferably monocrystalline) silicon layers that enable very small vertical interconnect manufacturing, and hence a large (>1 million/cm2) layer to layer vertical interconnect density in the stack. This opens up the possibility for powerful new architectures and devices, such as Amdahl’s wafer scale computer (see blog, website, technology) and cost effective MLC 3D memories.

Two implications arise from the thin (on the order of 100nm or less) silicon layer stacking. First, that fully depleted (FD) devices, and hence silicon islands floating in an insulator such as silicon dioxide, will be the norm. Second, taking full advantage of a manufacturable aspect ratio etching (5:1 to 10:1), we will end up with a large density of very small layer to layer vias (of 1-2 lambda diameter), where vertical interconnect density rivals the horizontal density of interconnect that we have enjoyed thru the many cycles of Dennard scaling.  FD devices are soon to be the norm in 2DICs; for example, the thin UTBBOX of STMicro/GlobalFoundries and the narrow FinFets of Intel/TSMC (incidentally, at IEDM12, Intel was criticized for doping the fins…).

Both of these implications, FD devices in islands of Si and very dense vertical interconnect, play a significant role in how we propose to solve a major challenge in 3D stacking. 

                                                           Since the stacked layers are not in direct contact with the heat sink:
                                                          How do we get the heat out of the stacked layers???


In short, the answer is to take the heat out of each silicon island with the power delivery network, move it laterally in the metal interconnect of that stack layer (just as if we had a thick silicon layer underneath), and then vertically move the heat to the heat sink with that large density of interlayer vias (which we can now make due to the thin stacked layer being very thin).

Here’s a picture of what we are doing:

Sounds at least plausible, right?

Well, that’s what we set out to show, with the heavy lifting done by our friends at Stanford. Hai Wei & Tony Wu of Professor Subhasish Mitra's group, Professor Mitra, and Professor Fabian Pease, were the drivers in creating the simulation approach and engine to see if this works as we thought it might. It did, and then ended up developing a tool that may be very useful for future 3DIC design work.

Hai and Tony describe in the paper and the presentation the details of the simulation approach, engine, assumptions, and methodologies developed. Quite a nice piece of work! They have built an analysis framework that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs. Types of 3DIC technologies modeled are conventional TSVs, called parallel 3D integration by many in the industry, and monolithic 3D integration, a type of sequential 3D integration. Cooling options range from conventional air cooling of the heat sink (2 W/K·cm2) to external liquid cooling (10 W/K·cm2) for high power systems. PDN designs studied ILV densities from 0 to 4 million/cm2.

That said, what are the essential takeaways?

First, the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Without accounting for PDNs in the 3DIC thermal model, it will be next to impossible to achieve the desirable thermal characteristics and result of a 3D IC stack. Further, the density of ILVs is important to achieving the system thermal constraint. In the 100nm thick Si example below, the desired maximum chip temperature is 85°C or less.

Second, a processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration. Hai and Tony’s thermal analyses of core-on-core and memory-on-core designs, utilizing the OpenSPARC T1 industrial multi-core design operating running an 8-threaded program that solves the Black-Scholes application (i.e., hot), showed significant improvement and no hot spots. The top silicon layer is 100nm thick and the hottest parts of the chips were operating at 138 W/cm2. Those hottest parts, the EXU units, were stacked directly on top of each other to show the worst case.

Combining these two seems to indicate that no PDN in the model versus designing and optimizing with thermal-aware PDNs makes the difference between being able to run the design (processor on processor in this example) at only 1/3 of the full power density or at a full power.

That’s the essential take-away for monolithic. Mimic the lateral heat conduction of thick silicon with the PDNs of the thin silicon stack layer, and then get that heat vertically to the heat sink with the dense network of vias provided by the monolithic 3D integration.

For the parallel 3D integration case, the 5um thick silicon greatly helps with the lateral heat conduction to the TSVs. With a properly designed PDN; however, there can be a significant savings in the number of TSVs (ILVs on chart below) used to vertically conduct the heat away, and thus offers a significant area savings by eliminating many of those big TSVs and Keep Out Zones (KOZs). (Note: for both the parallel and monolithic cases, Hai made the KOZ twice the ILV diameter as a conservative choice)

Moreover, by use of a properly designed PDN and an optimized density of TSVs, the maximum power density of the top layer in can be increased considerably …. from 35 to 50 W/cm2 for the parallel 3D case.

It is worth noting an important point from these graphs: At the optimum design point, where the density of ILVs coupled to the PDN satisfies the desired 50W/cm2 max allowed power density, the required number of TSVs to effectively conduct the heat costs about 3% of the chip area. For the monolithic case, the chip area cost is about half that. 

A high density of small vias not only makes possible some powerful product architectures such as logic-cone level redundancy, but is also key to producing area efficient vertical heat conduction networks.

BC

*Patent Pending technology

The EE Times article covering Imec's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase—and still carry a hefty cost premium—due to the lack of next-generation lithography". Van den Hove provided the following slide photo as an illustration:

Yet, in an article about Intel’s 22nm IEDM presentation, EE Times is quoting Mark Bohr of Intel: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said. “Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.


So who is right between those two giants?

Could it be that both of them are?

In a recent blog titled "Is the Cost Reduction Associated with Scaling Over?" we presented charts clearly supporting Luc van den Hove, IMEC's CEO, position. The following slide from an IBM presentation includes an NVidia chart (which we also discussed in another blog, Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? ).

Accordingly, it would seem that TSMC wafer costs are in line with Luc and so is the case with IBM.

GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium yesterday (Dec. 11) also acknowledged that their 14nm node will have a 20nm node metal pitch and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
In other words, it seems that the Luc van den Hove keynote is in-line with the cost road map of the non-Intel foundries!

Intel might indeed be different, yet something did cause Intel to take what seems like an extreme measure, when it put $4.1B in ASML just recently.

If, however, Mark Bohr has not been misled by the Intel accounting department, and the Intel process is still providing a nice cost reduction at every node of scaling, then clearly Intel has a true competitive edge relative to all other foundries. I have no doubts that Intel has filed enough patents to protect its unique process advantage, but then I wonder why did Mark say: "However . .. we don’t intend to be in the general-purpose foundry business … [and] I don’t think the [foundry] volumes ever will be huge [for Intel].”
If Mark Bohr is right, with such a competitive edge Intel should aggressively expand its foundry business, which would achieve both a great profit margin and rapid business growth. Now that Intel is looking for a new CEO its Board should consider it as a major criterion for who should lead Intel into the future.

P.S.

Clearly, dimensional scaling (and its cost reducing benefits) is not what it used to be, and the market appetite for cheaper-faster-better consumer-oriented products grows stronger. Both Intel and non-Intel fabs should start development of monolithic 3D technology.  ;-)

On Nov 9, 2012 we learned that Qualcomm overtook Intel in market capitalization. Quite shocking news if one considers that Intel’s revenue is almost three times that of Qualcomm and its net margin is more than twice that of Qualcomm. Clearly investors evaluate Qualcomm using a different scale than what they use for Intel, as is evidenced by Qualcomm’s P/E of 20.12 vs. Intel's mere 9.07. EE Times explained it in an article that day stating: "In the eyes of investors who have driven up its market capitalization, the fact that Qualcomm is a fabless company relieves it of the burden of having to invest billions of dollars each year in process development and wafer fabs." However, given that TSMC, a pure foundry, has a P/E of 15.67, it behooves us to look for another explanation. It’s also worth noting that TSMC had a revenue growth of 2% in the last year, far less than Intel's 25.6%, and its net income actually went down vs. a net income growth by Intel of 213%!

My explanation is that it is all about IP strength. I will expand on it in the rest of this blog but as prime evidence I offer SanDisk, who sports a P/E of 20.78  yet has continued to invest heavily, together with its partner Toshiba, in fab capacity upgrades.

Let’s first look at the previous two decades as Intel grew consistently year after year while riding the PC business growth. During those years the team Intel + Microsoft was the exclusive vendor in the PC 'game'. All others had to compete neck to neck in this fast growing commodity market.  And as we all know, broad competition erodes margins and allows only the lowest cost producer to achieve some profits. In the case of PC this erosion actually pushed out the market creator - IBM - which eventually exited the market and sold its business to Lenovo. The only real winners back then were Microsoft and Intel, who had pivotal differentiating IP. Yes, Intel had a licensor - AMD - but as a licensor, AMD had to pay heavy royalties that impacted its profits, and helped those of Intel.

Both Intel and Microsoft were able to leverage there unique IP into years of growth and became the largest companies in their field.

But being the largest today does not guarantee the tomorrow. Or, as Andy Grove famously said, "only the paranoid survive".

The technology world is about change. While many of the changes are incremental, at times the paradigm changes too. The change that took away Intel’s and Microsoft’s unchallenged market and IP position was the shift to "smart mobile," or mobile internet, as is illustrated in the following chart.

And with these changes new technology leaders have been emerging: companies such as  Apple, Qualcomm, and Google.

To make matters even worse, a small company - ARM - was able to create a disruptive change in the computing engine with its preferred computing architecture, first for 'smart mobile,' then for tablets, and now it seems to penetrate the PC and the server markets.

In my view, as soon as the investment community realized that Intel’s exclusive market and IP position is not relevant to the new market of Mobile Internet, it started to tune down Intel’s P/E. This trend even got stronger as investors became concerned regarding Intel’s position in the PC and server market.

It should be noted that in this context IP is not counted by the number of patents or the amount of trade secrets but rather by the ability to exclude competitors from major markets or extract royalties from those competitors, which may make you a winner even when you loose business. This is a status that Qualcomm and other companies such as SanDisk enjoy.


Economists estimate that two-thirds of the value of large businesses in the U.S. can be traced to intangible assets.[18] "IP-intensive industries" are estimated to generate 72 percent more value added (price minus material cost) per employee than "non-IP-intensive industries".[19][dubious – discuss] , as is illustrated by the following chart

So, is the game over for Intel??? Is the Market irrational, or is the Market perceptive?

Some pundits clearly think so, but given its leadership semiconductor technology, strong leading edge manufacturing infrastructure, and balance sheet, it is way too soon to call game over for Intel. But it would seem that Intel needs to introduce some real change in order to correct its course. Perhaps Intel should look back at what Andy Grove’s said and ask itself: does it really act like a paranoid company, or perhaps it is just the inverse.

We at MonolithIC 3D believe that the whole semiconductor industry is about to go through a major disruptive change. After 50 years of successful growth and progress by dimensional scaling, the time has come for a direction change, and the time is now for starting to embrace scaling-up, going for monolithic 3D. The current leaders in dimensional scaling, the NAND Flash vendors, seem to be leading the way. They are pushing ahead with monolithic 3D-NAND. This disruptive change will bring vast new opportunities, and those who will be early to embrace the change may be able to reap the IP reward.

The semiconductor industry is in the doldrums. The PC market shrinks, Intel shares sink, Applied Materials cuts staff, and even Apple suddenly experiences its share price drop by $100 in a month. Are things really so bad?

But other news seems different. TSMC shares are close to their historical high; Global Foundries leapfrogs TSMC technology and nips at Intel’s heels with 14nm; Samsung reports record quarterly profit. Things seem to be going swimmingly.

Semiconductor business has had its ups and downs since its inception. As demand followed, more and more capacity was put on line, which caused the next overcapacity and slump, inevitably followed by the next spike in demand as the technology inexorably marched down the scaling curve. So, perhaps, nothing is really new here after all.

Yet, perhaps, we should not be so sanguine anymore. We did cope with 193nm light to define our chips down to 20 nm, but at an ever-increasing cost of expensive phase shift masks, immersion lithography, and double exposure. EUV has been talked about for at least 15 years (following another 15 years of x-ray lithography development fiasco) and has been “late” since at least 2005. Despite the impressive progress shown by ASML, the industry greats – Intel, Samsung, and TSMC --banding around EUV is possibly more a sign of desperation than a strong vote of confidence. The drastic reduction in foundry players – from 20 or so in 90nm to four or less for 14nm has been noticed by many and cannot be good for the long-term health and vitality of the industry. 

ASML is the last remaining game in town and, even if it works, building a foundry at over $10B a pop, and developing a technology node at well north of $1B, does wonders at keeping everyone but the most committed (and with deep pockets) out of the game. And the unanswered question is still in place: at what price point will the industry effectively become the domain of the few mass-produced designs such as Apple’s or Samsung’s phones and nothing else? 

Clearly pressures have been building up and the industry can’t pretend everything is as usual for much longer.  3D devices has been talked about for decades, yet implementing this dream was considered infeasible until recently. 3D designs are, in a sense, the holy grail of the industry:

• They allow for shrinkage of the average source to destination distances, shrinking power dissipation and improving performance;
  

• They allow efficient heat removal without exotic cooling technologies through use of power delivery networks, to be presented in the upcoming IEDM, paper 14.2 ;
  

In recent years TSVs started to show up. Yet, while TSVs are good for designs that need limited vertical connectivity between disparate sub-systems such as processors with memory, they do not really open the door to a true monolithic 3D design.  What true monolithic devices offer is a much higher vertical connectivity, by a factor of up to 10,000, and enable the stacking of multiple dies.

The impact of the increased monolithic vertical integration at lower cost can be dramatic on every electronic market segment.

For mobile devices, the inexpensive integration of analog, RF, and sensors, can lower their cost and power consumption for an even broader market penetration and longer battery life.

In medicine, the footprint of devices is often critical. The availability of camera-in-a-pill, or of implantable medical devices that control drug release, improve hearing, monitor vital signs, or allow artificial vision, are all strongly dependent on heterogeneous device integration in a small footprint and with reduced power. Monolithic 3D is key to transforming the planar and bulky designs of today’s 2D to grain-of-corn and grain-of-rice shape factors that can be inserted for very long time periods into our bodies.

Fostering innovation and reducing barriers to entry of new products are considered crucial for future economic prosperity. FPGAs have been trying to fill this niche since the demise of ASICs, yet they suffer from many handicaps: they are physically large, they are power hungry, and they are available in a limited number of configurations that are often suboptimal for the application. Monolithic 3D technology allows the inexpensive creation of a nearly infinite number of FPGA configurations that can be tailored to every application, as described here. And it does so while dramatically reducing both the device footprint and power.

Large-scale computing is facing enormous challenges to reduce its power consumption. Server farms of the likes of Google, Amazon, or Facebook consume tens and hundreds of megawatts of energy, while the government struggles mightily to keep its planned Exascale supercomputer under 20MW. Three-dimensional chips can play a large role in reducing power consumption by reducing the interconnect length (and hence, its capacitance), which is responsible for most of the power dissipation in modern chips. Ultra large scale integration with high yields, enabled through 3D repair structures, will further slash the power that today resides in the off-chip drivers.

In memory design, the transition to 3D technology is already taking place as described in our previous blog. Monolithic 3D structures using crystalline silicon may further the penetration and efficacy of this technology in both non-volatile memory as well as in DRAM.

The semiconductor world will inevitably move to monolithic three-dimensional technologies. The change drivers are already here: the skyrocketing cost of scaled-down lithography, the need to reduce power dissipation, and the need for heterogeneous integration. The only question is how quickly it will move there, and who will be the winners.

NAND technology, which is a subset of NVM (Non Volatile Memory), was invented by Fujio Masuoka of Toshiba back in 1984. Flash memory was presented at IEDM1984 by Dr. Masuoka and his colleagues [1].  The following is a short quote from the original paper “the cell is programmed by a channel hot carrier injection mechanism similar to EPROM. The contents of all memory cells are simultaneously erased by using field emission of electrons from a floating gate to an erased gate in a FLASH (Hence the name FLASH)”.  

Masuoka came back to the IEDM in 1987 and suggested a Flash NAND structure [2].
Intel created the first commercial NOR type of Flash chips in 1988. For the next few years some major developments occur in the Flash arena:

• In 1989, Samsung and Toshiba created a NAND flash memory.
• In 1994, Compact Flash was invented and introduced by SanDisk.
• In 1999, the SD memory card was released by a combination of SanDisk, Toshiba and Matsushita.
• In 2001, the world’s first 1 Gigabit Compact Flash card was introduced.

From 2006 onwards, NAND became the most scaled of devices beating out the microprocessor devices (see Figure 1). The current state of the art is 20nm (2x) technology, as the world’s appetite for storage is still strong. Flash Cards, SSD, Smartphone and Tablets are the leading growing applications.

NAND memory as a true cross point array with the control gate on top of the floating gate and only one contact for a whole string of cells has the smallest memory cell size as shown in Figure 2 In addition, when one adds with the capability of MLC (Multi Level Cells) to NAND devices, the bit density dramatically increases.

The NAND market has been continuously growing for the last several years. Figure 3 shows the NAND revenue and Gigabytes increase since 2008 and the forward projection for the years 2012-2016.

As the NAND technology has been moving to smaller and smaller process nodes some serious problems, physical and electrical surfaced:
           Physical Limitations:

• Pattern scaling - lack of EUV is a major issue
• Structure formation, Figure 4 depicts a 27nm NAND cell that shows how close the cells are getting to each other, and how much the aspect ratio is getting out of hand. This is a limiter to obtaining high yield.

          Electrical Limitations:

• There is an increase in cell-to-cell interference in the word lines.
• Capacitive coupling ratio has decreased
• Dielectric leakage has increased

The number of electrons on the floating gate has decreased dramatically so much so that a small fluctuation in the number on the floating gate can make a huge effect on the cell function. Figure 5 describes the scaling induced phenomenon.

It is a common understanding among the experts that the current NAND technology will not be able to be scaled down to the 10nm node.

The solution for this dilemma is the 3D NAND, which was initially proposed by Toshiba at the 2007 VLSI Symposium [3]. Toshiba unveiled its Bit Cost Scalable (BiCS) technology. BiCS makes use of a “punch-and plug” structure and charge trap memory films. Toshiba has fabricated a prototype 32-Gbit BiCS flash memory test array with a 16-layer memory cell using 60nm design rules, see Figure 6. Hynix, Samsung and Macronix have also come with their versions of the 3D NAND.

The following are the key advantages of the 3D NAND:

• With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition
  
• The key steps to 3D NAND are
  

                                        - Build a multitude of oxide/nitride or oxide/doped polysilicon stacked layers
                                - Fill the deep memory holes or trench slits. The top foreseeable challenges are ultra-high-aspect ratio (>40:1) conductor etch and dielectric etch with high etch selectivity to the hard mask

• 3D NAND is relatively straightforward for a DRAM maker since it has stacked SiO2 and polysilicon layers like a stacked capacitor DRAM, and trenches like a trench cell DRAM. 
  
• 3D NAND is evolutionary, not revolutionary. 
  
• The good news is continued cost reduction, smaller die sizes and more capacity. 
  
• Installed NAND toolsets in the wafer Fabs can, for the most part, be reused, thereby extending the useful life of Fab equipment. 
  
• 3D NAND technology is still basically NAND with all its inherent limitations of data reliability and performance: hence, generally well understood (evolutionary).
  

At this point all the NAND companies are putting a lot of effort to bring this process to high volume manufacturing; the current expectations are that in 2014-2015 it will be ready for prime time. 3D NAND will be a technology that will take us between the 2D planar NAND and whichever post-NAND technology emerges in the future.

Figure 7 describes the essence of the advantage of moving from 2D to 3D NAND. The adoption of 3D NAND technology will remove the burden from the Litho (and hence EUV) into the much easier process steps (deposition). Of course there are other advantages as described above.

It is not too difficult to see the similarity between the up and coming 3D NAND and the Monolithic 3D approach. As we describe in our web site (www.monolithic3d.com) the advanced technology patented by MonolithIC 3D Inc. enables the fabrication of Monolithic 3D Integrated Circuits with multiple stacked transistor layers and ultra-dense vertical connectivity. Thus, it appears monolithic 3D-ICs with 2 device layers provide benefits similar to a generation of conventional scaling. Furthermore, just as conventional scaling reduces feature sizes every generation, monolithic 3D opens the road for many years of continuous scaling by ‘folding’ once, twice, and so forth without necessarily reducing feature sizes.

1. F. Masuoka et. al IEDM 1984 pp464-467
2. F. Masuoka et. al IEDM 1987 pp552-555
3. H. Tanaka et al., Symp. on VLSI Tech. Dig., pp 14-15, 2007

Thanks to everybody who came by our booth at SemiconWest SemiconWest 2012 this second year! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.

For those who could not make it, here is what our booth looked like:

Nice tie again Zvi! You can still visit us at www.monolithic3d.com.

The most common area that you asked us was about low temperature (less than 400°C) bonding and low temperature cleaving processes. The two topics are quite inter-related: One must make the bond stronger than the energy it takes to cleave at the plane you want, rather than cleave at th at fresh bond. In October last year I wrote a blog about the many low temperature bonding techniques and strategies available and their respective bond strengths. Today, I would like to briefly address some of the low temperature cleaving methods available. Generally they involve either a mechanically induced (blade, gas jet, water jet) method, a lower temp thermal (co-implantation, microwave, etc.) cleaving/layer-transfer method, or a combination of both.

Here are a few papers, with some industrial announcements at the end.

One of the earliest methods published is co-implantation by Q.Y. Tong et al. of Duke University at the 1997 IEEE SOI Conference.  Tong could greatly affect the kinetics of the hydrogen blister formation by co-implantation of Boron. They were able to transfer a 0.4um silicon layer onto a quartz substrate with a 150°C exposure to the quartz by pre-annealing the co-implanted silicon for 10 minutes at 250°C.

Tong with colleagues at the Max-Planck-Institute followed up with more co-implantation

kinetics data in a 2008 Applied Physics Letter. They again demonstrated a 200°C silicon cleave.


In 1998 App. Phys. Lett., Agarwal et al. showed that He implanted with the H could lead to a significant decrease in the total implant fluence (and hence cost) necessary to achieve Si layer transfer. The total implantation dose can be three times smaller than that which is necessary using H alone.

Nguyen et al. of Soitech/CEA-Leti, at the 2003 IEEE SOI Conference showed that He co-implantation could be used to control the kinetics, so time, dose and temperature trades could be made.

Ma, et al. showed in Semcond Sci. Technol. 2006 that a co-implanted cleave has a smoother

surface than a hydrogen-only implanted cleave.

In 2000 App. Phys. Lett., Henttinen et.al showed mechanical cleaving, blade or N2 gas, on low temperature bonded silicon wafers (ox-ox bond). Depending on the H dose, Henttinen could

cleave the silicon wafers at 200°C or 300°C. Henttinen et.al followed up later in 2002 in J. Nucl. Instr. and Meth. in Phys with fundamental mechanistic studies and also demonstrated that with enough B doping one can enable H-implanted layer exfoliation below 200°C.

Cho et al., in 2003 App. Phys. Lett. reported that full wafer layer transfer could be achieved with a mechanical cleave (edge initiated crack propagation) after a 250°C annealing that enabled the bonding strength at the acceptor/donor interface to exceed the required cleave energy at the hydrogen implant plane.

En, et al., of Silicon Genesis, described a room temperature H implant using PLAD (Plasma Immersion Ion Implantation), plasma assisted oxide to oxide bonding, and a room temperature mechanical cleave process at the 1998 IEEE SOI Conference.

Current, et al. of Silicon Genesis, showed a wafer separation tool in MRS 2001 where they utilized a pressurized N2 jet to cleave silicon bonded pairs at room temperature.

Recently from the industrial side:

Soitec announced at SemiconWest 2012 the availability of a room temperature smart cut:
"Soitec’s low-temperature Smart Cut process uses oxide-oxide molecular bonding and atomic-level cleaving to transfer mono-crystalline silicon films as thin as 0.1 micron onto partially or fully processed wafers. On this new material layer, a second level of devices can be processed and this integration can be repeated in an iterative mode. Transferring an extremely thin layer enables higher interconnect density, higher signal throughput and simpler TSV processing. Benefits include increased computing bandwidth, lower overall manufacturing cost, and power savings due to the reduced wiring distance between connected devices. This final benefit is well suited for producing advanced memory or CMOS logic 3D IC systems.” See: http://www.soitec.com/en/news/press-releases/article-346/

SiGen (Silicon Genesis) has tools (some shown above) available that will bond and cleave at or near room temperature: http://www.sigen.net/semi_debondCleave.html

References:

TONG, Q.-Y., et al., "Low Temperature Si Layer Splitting", Proceedings 1997 IEEE International SOI Conference, Oct. 1997,  pp. 126-127

TONG, Q.-Y., et al., "A ‘‘smarter-cut’’ approach to low temperature silicon layer transfer", Applied Physics Letters, Vol. 72, No. 1, 5 January 1998, pp. 49-51 

AGARWAL, A., et al., "Efficient production of silicon-on-insulator films by co-implantation of He+ with H+'" Applied Physics Letters, vol. 72, no. 9, March 1998, pp. 1086-1088.

NGUYEN, P., et al., "Systematic study of the splitting kinetic of H/He co-implanted substrate",  SOI Conference, 2003, pp. 132-134

MA, X., et al., "A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding", Semiconductor Science and Technology, Vol., 21, 2006, pp. 959-963

HENTTINEN, K. et al., "Mechanically Induced Si Layer Transfer in Hydrogen-Implanted Si Wafers," Applied Physics Letters, April 24, 2000, p. 2370-2372, Vol. 76, No. 17.

HENTTINEN, K. et al., "Cold ion-cutting of hydrogen implanted Si," J. Nucl. Instr. and Meth. in Phys. Res. B, 2002, pp. 761-766, Vol. 190.

CHO, Y., et al., “Low Temperature Si Layer Transfer by Direct Bonding and Mechanical Ion Cut,” Applied Physics. Letters., vol. 83, no. 18, November 2003, pp. 3827-3829.

EN, W. G., et al., “The Genesis ProcessTM: A New SOI wafer fabrication method”, Proceedings 1998 IEEE International SOI Conference, pp. 163-164 (Oct. 1998).

CURRENT, M. I., et al., “Atomic-layer Cleaving and Non-contact Thinning and Thickening for Fabrication of Laminated electronic and Photonic Materials”, 2001 Materials Research Society Meeting, April 16-20 2001, Paper I8.3.

The last 50 years of the semiconductor industry have been all about the manifestation of Moore's Law in dimensional scaling of Integrated Circuits (ICs). As consumers of electronic devices we all love to see with every new product cycle better products at a lower cost. But now storm clouds are forming, as was recently publicly expressed "Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless".

Clearly dimensional scaling is no longer associated with lower average cost per transistor. The chart below, published by IBS about a year ago, shows the diminishing benefit of cost reduction from dimensional scaling. In fact, the chart indicates that the 20nm node might be associated with higher cost than the previous node.

The following Nvidia chart provides the first order explanation. The cost reduction of dimensional scaling resulted from doubling the number of transistors per wafer. But if the wafer cost of the new technology node increases by too much then it neutralizes that cost reduction. The Nvidia chart shows the wafer cost of recent nodes over time. In the past (...80nm, 55nm, 40nm) the incremental wafer cost increases were small and rapid depreciation of those costs resulted in almost constant average wafer price. Recent nodes (28nm, 20nm, 14nm, ...), however, signal a new reality.

The following busy slide of IBM summarizes it clearly: "Net: neither per wafer nor per gate showing historical cost reduction trends"

The number one driver to the increase of wafer cost is the increase in the equipment cost required for processing the next technology node. The following chart presents the increase in costs of capital, process R&D, and design.

The sharp increase of costs associated with scaling is a new phenomenon. There were always costs to move from one node to the next, but they were about constant or incrementally small.

The following slide presents the innovations that enable dimensional scaling. Clearly, for many nodes we were able to use the same lithography tools. But once dimensional scaling reached the limit of light wavelength the lithography tool became critical and dominant. About for every node the lithography became a major challenge that required newer equipment and substantial process R&D. Moreover, in the recent lithography nodes the transistor itself required significant innovation at every node (high-k, Metal Gate, Strain, SiGe, Tri-gate,...) and it is clear that future scaled nodes will require even more of those innovations and their associated costs.

An important part of these costs is the escalating cost of the capital equipment for the next node fabrication lines. The following figure present the cost dynamic for the lithography equipment. Note the logarithmic scale of the cost axis.

Lithography tools grew from less than 10% of wafer fab equipment (WFE) spending to over 25% and accordingly lithography now represents about 50 % of the wafer cost.

An interesting implication of growing domination of lithography in semiconductor processing is the fact that the ASML, which is the lead vendor of lithography tool, recently passed Applied Material’s (the leader of all other tools) market cap. Following is the chart of the stock price of ASML (in red) vs. Applied Material (AMAT).

The clear conclusion of all of this is that future dimensional scaling is not about to change these trends. Accordingly, as stated in the IBM slide above: "Net: neither per wafer nor per gate showing historical cost reduction trends."  Unless ...


Unless we change the way we do scaling (remember Einstein’s famous quote). Moore’s Law is about doubling the number of transistors in a semiconductor device. At that time dimensional scaling was one of the three trends Moore described that would enable the observed and predicted exponential increase of device integration. It would seem that it is about time to look on another one of those - increasing the die size. If we do it by using the 3rd dimension – monolithic 3D-IC – we can achieve both higher integration and cost reduction!

It is not that we should stop scaling down, it just that if we augment it with scaling up we can introduce the required changes that can achieve the continuation of the cost reduction trend. Clearly almost all of the increases of wafer costs are related to the pace of dimensional scaling. If those costs could be spread over four years instead of two then the increase in wafer cost would be only about half of what it is now.

It might not be so clear, however, why monolithic 3D should reduce wafer cost. Shouldn’t the cost of the double die size spread over two layers be at least double …?

Monolithic 3D IC would reduce wafer cost because of the following elements:

            1. Reduced Die Size - It has been shown in many research studies that each folding into 3D has the potential to reduce the total required silicon area by 50% due to the reduced re-buffering and reduced sizing of the buffers.

            2. Depreciation - Scaling up enables the use of the same fab and process R&D for few additional years with the associated improvement in deprecation costs and improved manufacturing efficiencies and yield.

            3. Heterogeneous Integration - Scaling up would enable heterogeneous integration. This will open up the third trend of Moore- improved circuit design. As each strata of 3D IC could be processed in a different flow, cost and power could be saved by using a different process flow for logic, memory and I/O.

            4. Multiple Layers Processed Together - This would be most effective for a memory type circuits. Using the right architecture, multiple transistors layers could be process simultaneously with the result of a huge reduction of cost per layer.

Let’s detail each of these.

Reduced Die Size

Dimensional scaling has always been associated with an increase of wire resistivity and capacitance. The industry had spent a huge effort to overcome these by first replacing the conducting material with copper and then changing the isolation material to low-K dielectrics. But the interconnect problem is still growing as demonstrated in the following chart.

Every node of dimensional scaling is associated with larger cells, output drivers, and more buffers and repeaters. Monolithic 3D enables one to fold the circuit where the next strata is about 1µ above with a very rich vertical connectivity between the strata. The following IBM/MIT slide illustrates the effectiveness of such folding.

Further, the reduced silicon area generates an additional reduction of buffers and the average transistor size. MonolithIC 3D Inc. released an open-source top level simulator IntSim v2.0 to simulate a given design’s expected size and power based on process parameters and the number of strata (more than 300 copies have been downloaded so far).

Using the simulator we can see in the following table that a design that uses 50 mm2 with average size gate size of 6 W/L, will need an average gate size of 3 W/L and accordingly only 24 mm2 if folded into two strata (the footprint will be therefore just 12 mm2). 

These results are in-line with many other monolithic 3D research results.

Depreciation

The semiconductor industry is very capital intensive and a very significant part of the wafer cost is associated with the cost of capital. Since every two years we have been scaling to a new node, then the wafer cost needs to support this rapid loss of capital value. Achieving the next level of device functionality using the same generation of tools allows for a far better utilization of the investment capital. In addition the learning curve of yield and manufacturing efficiency contributes further to the end-product cost reduction. The following chart portion demonstrates this well known trend.

Heterogeneous Integration

Let’s start with quoting Mark Bohr, in charge of Intel’s process development:

"Bohr: One important perspective is that chip technology is becoming more heterogeneous. If you go back 10 or 20 years ago, it was homogenous. There was a CMOS transistor, it was the same materials for NMOS and PMOS, maybe different dopant atoms, and that basic CMOS transistor fit the needs of both memory and logic. Going forward we’ll see chips and 3D packages that combine more heterogeneous elements, different materials, and maybe transistors with very different structures whether they’re for logic or memory or analog. Combining these very different devices onto one chip or into a 3D stack—that’s what we’ll see. It will be heterogeneous integration"

The most important market for semiconductor products is smart mobility. For this market the SoC device needs to integrate many functions. In most cases the pure high-performance logic would be about 25% of the die area, 50% would be memories and the rest would be analog functions such as I/O. In 2D they all need to be processed together and bear the same manufacturing costs. In a monolithic 3D-IC stack using heterogeneous integration each stratum is processed in an optimized flow, allowing for a significant cost reduction. The following illustration suggests the use of only two strata to build a device that in 2D would have a size of 196 mm2. By having one stratum for logic and one for memory, and by using DRAM instead of SRAM, the device could be reduced to 98 mm2 with footprint of 49 mm2. The device cost would be further reduced by the memory using only 3 or 4 metal layers.

Multiple Layers Processed Together

Using the right architecture, multiple transistor layers could be processed together with a huge reduction in cost per layer. This could be applied to many different types of regular devices.

The following illustrate the concept with respect to a floating-body DRAM:

MonolithIC 3D Inc’s website presents more details for the DRAM flow, and also related flows for RRAM and NAND Flash memories.

In short, we do have a path to continue the semiconductor industry drive for better products and with lower costs, but we should continuously apply innovation to do so. Now that monolithic 3D is practical, it is time to augment dimension scaling with monolithic 3D-IC scaling.